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vt1621 and VT1621M tv encoder revision 1.0 june 17, 2002 via technologies, inc. ( datasheet : )
copyright notice: copyright ? 2001, 2002 via technologies incorporated. printed in the united states. a ll r ights r eserved . no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise without the prior written permission of via technologies incorporated. vt1621 and VT1621M may only be used to identify a product of via technologies, inc. is a registered trademark of via technologies, incorporated. windows 98 tm , windows nt tm , windows 2000 tm , and plug and play tm are registered trademarks of microsoft corp. pci tm is a registered trademark of the pci special interest group. all trademarks are the properties of their respective owners. disclaimer notice: no license is granted, implied or otherwise, under any patent or patent rights of via technologies. via technologies makes no warranties, implied or otherwise, in regard to this document and to the products described in this document. the information provided by this document is believed to be accurate and reliable to the publication date of this document. however, via technologies assumes no responsibility for any errors in this document. furthermore, via technologies assumes no responsibility for the use or misuse of the information in this document and for any patent infringements that may arise from the use of this document. the information and product specifications within this document are subject to change at any time, without notice and without obligation to notify any person of such change. offices: usa office: taipei office: 940 mission court 8 th floor, no. 533 fremont, ca 94539 chung-cheng road, hsin-tien usa taipei, taiwan roc tel: (510) 683-3300 tel: (886-2) 2218-5452 fax: (510) 683-3301 or (510) 687-4654 fax: (886-2) 2218-5453 http://www.viatech.com http://www.via.com.tw
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 -i- revision history technologies, inc. we c onnect w e c onnect we c onnect w e c onnect r evision h istory document release date revision initials 1.0 6/17/02 initial public release ey
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 -ii- table of contents technologies, inc. we c onnect w e c onnect we c onnect w e c onnect t able of c ontents revision history ............................................................................................................... ........................................................ i table of contents .............................................................................................................. ....................................................ii list of figures................................................................................................................ ......................................................... iii list of tables................................................................................................................. .......................................................... iii product features ............................................................................................................... .....................................................1 overview ....................................................................................................................... ................................................................2 pinouts ........................................................................................................................ ....................................................................3 p in d iagram ............................................................................................................................... ..................................................3 p in l ist ............................................................................................................................... ...........................................................4 p in d escriptions ............................................................................................................................... ..........................................5 registers ...................................................................................................................... .................................................................6 r egister o verview ............................................................................................................................... .....................................6 r egister d escriptions ............................................................................................................................... ...............................7 functional description......................................................................................................... ............................................13 a rchitecture d escription ............................................................................................................................... .....................13 data capture ................................................................................................................... ......................................................13 color space converter .......................................................................................................... ...............................................13 scaler and deflicker........................................................................................................... ...................................................13 encoder ........................................................................................................................ ..........................................................13 dac............................................................................................................................ ............................................................13 serial bus interface ........................................................................................................... ....................................................14 crtc ........................................................................................................................... ..........................................................14 pll............................................................................................................................ .............................................................14 m aster /s lave c lock m ode ............................................................................................................................... ....................14 master mode .................................................................................................................... ......................................................14 slave mode..................................................................................................................... ........................................................14 digital video interface........................................................................................................ ..................................................16 video standards ................................................................................................................ ....................................................17 color bar test pattern generator............................................................................................... ........................................27 subcarrier generation.......................................................................................................... ................................................27 burst generation............................................................................................................... ....................................................27 power down mode ................................................................................................................ ................................................27 macrovision anti-copy protection............................................................................................... .......................................27 display modes .................................................................................................................. .....................................................27 filters ........................................................................................................................ .............................................................30 clock frequency ................................................................................................................ ...................................................32 pc board layout considerations ................................................................................................. ...............................33 c omponent p lacement ............................................................................................................................... ............................33 electrical specifications ...................................................................................................... .........................................34 a bsolute m aximum r atings ............................................................................................................................... ...................34 r ecommended o perating c onditions ............................................................................................................................... ..34
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 -iii- table of contents technologies, inc. we c onnect w e c onnect we c onnect w e c onnect p ower s upply c urrent and t otal p ower c onsumption s pecifications ....................................................................35 dc s pecifications ............................................................................................................................... .....................................35 dac dc c haracteristics ............................................................................................................................... .......................36 dac ac c haracteristics ............................................................................................................................... .......................36 d isplay s ignal c haracteristics ............................................................................................................................... ...........37 pll c haracteristics ............................................................................................................................... ...............................37 package mechanical specifications .............................................................................................. ..........................38 l ist of f igures figure 1. functional block diagram............................................................................................ ..............................2 figure 2. pin diagram (top view) .............................................................................................. .......................................3 figure 3. master clock mode 1................................................................................................. .....................................14 figure 4. master clock mode 2................................................................................................. .....................................15 figure 5. slave clock mode .................................................................................................... ........................................15 figure 6. input interface protocol ............................................................................................ ..............................16 figure 7. interlaced 525-line (ntsc) video timing............................................................................. .................18 figure 8. interlaced 525-line (pal-m) video timing ............................................................................ ...............19 figure 9. interlaced 625-line (pal-b, d, g, h, i, nc) video timing (fields 1-4)..........................................20 figure 10. interlaced 625-line (pal-b, d, g, h, i, nc) video timing (fields 5-8)........................................21 figure 11. interlaced 625-line (pal-n) video timing (fields 1-4).............................................................. ....22 figure 12. interlaced 625-line (pal-n) video timing(fields 5-8)............................................................... ....23 figure 13. 525-line (ntsc/pal-m) y (luma) video test pa ttern waveform .............................................24 figure 14. 625-line (pal-b, d, g, h, i, n, nc) y (luma) test pa ttern waveform.........................................24 figure 15. 525-line (ntsc/pal-m) c (chroma) video test pa ttern waveform.......................................25 figure 16. 625-line (pal-b, d, g, h, i, n, nc) c (chroma) video test pa ttern waveform ....................25 figure 17. composite 525-line (ntsc/pal-m) video test pa ttern waveform........................................26 figure 18. composite 625-line (pal-b, d, g, h, i, n,nc) video test pa ttern waveform ......................26 figure 19. luminance lowpass filter response (27 mhz)......................................................................... .......30 figure 20. chrominance lowpass filter response (27mhz) ........................................................................ ..31 figure 21. ground plane with 4 layer pcb...................................................................................... ........................33 figure 22. mechanical specification ? 44-pin tqfp thin quad flat pack .............................................38 l ist of t ables table 1. pin list (alphabetical order) ........................................................................................ ...............................4 table 2. pin descriptions ..................................................................................................... ................................................5 table 3. register summary..................................................................................................... ...........................................6 table 4. input data format .................................................................................................... .........................................17 table 5. display modes for pal (m)............................................................................................ ..................................27 table 6. display modes for ntsc (m, j) & pal (b, d, g, h, i, n, nc) ........................................................... .........29 table 7. clock settings ....................................................................................................... ..............................................32
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 -1- product features technologies, inc. we c onnect w e c onnect we c onnect w e c onnect vt1621 and VT1621M tv encoder product features tv output supporting inputs up to 800x600 graphics resolutions supports digital rgb (15/16 or 24-bit) or ycrcb (ccir601 or ccir656) 16 bit 4:2:2 input video data in both interlaced or non-interlaced formats supports ntsc(m and j) or pal (b, d, g, h, i, m, n and nc) tv output standards supports macrovision 7.1 anti-copy protection (VT1621M only) underflow check and coring function for reducing the input noise composite, s-video and scart output support flicker filtering to enhance to tv image quality dot crawl control circuit to still this phenomenon master or slave video timing operation new algorithm for text sharpness high quality 3 x 9-bit video dac serial bus programming interface programmable power management automatic detection of tv presence buffered crystal clock output pin proscale ? ? ? ? engine support for underscan and overscan mode 44-pin tqfp package
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 -2- overview technologies, inc. we c onnect w e c onnect we c onnect w e c onnect o verview the vt1621 and VT1621M are television encoders that accept various rgb or ycrcb pixel data streams from a vga controller or mpeg decoder and generates high quality flicker-free composite and y/c (s-video) signals. both of these chips contain the same functionality and register. the only variation is that the vt1621 is macrovision disabled and the VT1621M is macrovision enabled. both of these chips can accept any digital input format from 512x384 to 800x600. the input data is also compliant wi th ccir656 and ccir601. these two tv encoder chips use via?s proscale technology to provide the most advanced vertical and horizontal scaling for the display of non-interlaced data on interlaced tv. this proscale technology also converts the lines of input video stream data t o an appropriate number of output lines for producing a full-screen high quality tv image. worldwide video standards are supported, including ntsc-m (north america, taiwan) ntsc-j (japan), pal-b, d, g, h, i (europe, asia), pal-m (brazil), pal-n (uruguay, paraguay) and pal-nc (argentina). the vt 1621m can output a video with the macrovision 7.1 anticopy included video signal. the macrovision anti-copy process provides a means to deter any unauthorized copying of copy protected analog video signals onto a videocassette. all features are software programmable throu gh a serial bus interface that provides read/write access to all registers. figure 1. functional block diagram data capture color space converter ntsc/ pal encoder dac crtc pll pd[11:0] scaler and deflicker y / r c / g cvbs / b serial bus interface sbd sbc hsync vsync xclk p_out pixel clock horizontal & vertical timing
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 -3- pinouts technologies, inc. we c onnect w e c onnect we c onnect w e c onnect p inouts pin diagram figure 2. pin diagram (top view) 1* 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 tv encoder tqfp 44 pd3 pd4 pd5 pd6 vcc25 pd7 pd8 gnd pd9 pd10 pd11 xo xi vccpll vcc33 reset# gnd sbc sbd vccdac rset gnddac vcc33 gnd testmode conf_xlt vcc25 csync gnd gnddac cvbs c y pd2 pd1 pd0 vsync hsync xclk vcc33 pclk gnd ds_bco gndpll note: 1. vcc25: 2.5v 2. vcc33: 3.3v 3. vccpll: 2.5v 4. vccdac: 2.5v
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 -4- pinouts technologies, inc. we c onnect w e c onnect we c onnect w e c onnect pin list table 1. pin list (alphabetical order) pin pin name pin pin name 21 o c 6 io pd7 15 i conf_xlt 7 io pd8 17 io csync 9 io pd9 20 o cvbs 10 io pd10 35 io ds_bco 11 io pd11 8 p gnd 29 i reset# 13 p gnd 24 i rset 18 p gnd 27 i sbc 28 p gnd 26 io sbd 36 p gnd 14 i testmode 19 p gnddac 5 p vcc25 23 p gnddac 16 p vcc25 34 p gndpll 12 p vcc33 40 io hsync 30 p vcc33 37 io pclk 38 p vcc33 42 io pd0 25 p vccdac 43 io pd1 31 p vccpll 44 io pd2 41 io vsync 1 io pd3 39 i xclk 2 io pd4 32 i xi 3 io pd5 33 i xo 4 io pd6 22 o y
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 -5- pinouts technologies, inc. we c onnect w e c onnect we c onnect w e c onnect pin descriptions table 2. pin descriptions signals signal name pin # type description pd[11-0] 11, 10, 9, 7, 6, 4, 3, 2, 1, 44, 43, 42 io input for pixel data. these inputs can accept 8 or 12 bit multiplexed rgb or ycbcr format. output for testing only. hsync 40 io when rx1[2]=0, this pin can accept a horizontal sync input. when rx1[2]=1, the device will output a horizontal sync pulse through this pin. vsync 41 io when rx1[3]=0, this pin can accept a vertical sync input. when rx1[3]=1, the device will output a vertical sync pulse through this pin. xclk 39 i reference clock for pds. it can operate on 1x, 2x or 3x pixel clock. pclk 37 io pixel clock output. this pin can provide and operate on 1x, 2x or 3x pixel clock to vga. input for testing only. ds_bco 35 io input for display enable. the rising edge of this signal identifies the first active pixel of data for each active line. output for providing a 14.31818 mhz clock to other devices. y 22 o luminance output for general tv system. c 21 o chrominance output for general tv system. cvbs 20 o composite video output for general tv system. csync 17 io composite sync. input for testing only. sbd 26 io serial bus data pin. sbc 27 i serial bus clock pin. testmode 14 i test mode enable. pull down for regular operation. conf_xlt 15 i selects internal or external oscillator. when pulled low, a crystal must be attached to pins 32 and 33. if pulled high, a stable 14.31818mhz external clock source must be supplied to pin 32, xi. reset# 29 i when this pin is low, the device is held in the power-on reset condition. xi 32 i a 14.31818 mhz crystal is attached between xi and xo. an oscillator can also be connected to this pin. xo 33 i a 14.31818 mhz crystal is attached between xi and xo. if an external oscillator is attached with xi, this pin should be connected to ground. rset 24 i an external resistor, typically 4.87k ? , attached between this pin and ground sets the fs (full scale) range of the dacs. power and ground signal name pin # type description vcc33 38, 30, 12 p i/o power. 3.3v gnd 13, 36 p i/o ground vcc25 5, 16, p digital power. 2.5v gnd 8, 18, 28 p digital ground vccpll 31 p pll power. 2.5v gndpll 34 p pll ground vccdac 25 p dac power. 2.5v gnddac 23, 19 p dac ground
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 6- register descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect r egisters register overview the following tables summarize the configuration and i/o registers that apply to the vt1621 and VT1621M tv encoder. these tables also document the power-on default value (?default?) and access type (?acc?) for each register. access type definitions used are rw (read/write), ro (read/only), ??? for reserved / used (essentially the same as ro), and rwc (or just wc) (read / write 1?s to clear individual bits). registers indicated as rw may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as rwc or wc may have some read-only or read write bits (see individual register descriptions for details). detailed register descriptions are provided in the following section of this document. all offset and default values are shown in hexadecimal unless otherwise indicated. table 3. register summary offset tv encoder registers default acc 00 input frame forma t 00 rw 01 input sync forma t 00 rw 02 scaling / chroma filte r 00 rw 03 luma filte r 00 rw 04 output mode 00 rw 05 control 1 00 rw 06 control 2 00 rw 07 start active video 00 rw 08 start horizontal positio n 00 rw 09 start vertical positio n 00 rw 0a cr amplitude facto r 00 rw 0b black level 00 rw 0c luma amplitude facto r 00 rw 0d cb amplitude facto r 00 rw 0e power management 00 rw 0f status 00 ro 10 special effect 0 00 rw 11 special effect 1 00 rw 12 pll p2 value 00 rw 13 pll d value 05 rw 14 pll n value 21 rw 15 pll overflo w 04 rw 16 sub-carrier value 0 00 rw 17 sub-carrier value 1 00 rw 18 sub-carrier value 2 00 rw 19 sub-carrier value 3 00 rw 1a - reserved - 00 ? 1b version id 02 ro 1c overflow 00 rw 1d test 0 00 rw 1e test 1 00 rw 1f test 2 00 rw 20 tv sync step 00 rw 21 tv burst envelope step 00 rw 22 tv sub-carrier phase adjustment 00 rw 23 tv blank level 00 rw 24 tv signal overflow 00 rw 25-49 - reserved - 00 ? 4a input aperture threshold 00 rw 4b input aperture delta 00 rw 4c aperture upper threshold 00 rw 4d aperture lower threshold 00 rw 4e aperture mode and del t a 00 rw 4f coring functio n 00 rw 50 y delay control 00 rw 51 uv delay control 00 rw 52 burst maximum amplitude 00 rw 53-ff - reserved - 00 ?
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 7- register descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect register descriptions offset 00 ? input frame format ..................................... rw 7-5 frame resolution 000 512x384................................................. default 001 720x400 010 640x400 011 640x480 100 800x600 * 101 720x576 (for pal) * 101 720x480 (for ntsc) * 110 800x500 (for pal) * 110 640x400 (for ntsc) 111 -reserved- * interlaced input mode 4 rgb pass through mode 0 disable................................................... default 1 enable 3-0 input data format 00xx -reserved-................................. default = 0000b 0100 12-bit multiplexed rgb (24-bit color) input (?c? multiplex scheme) 0101 12-bit multiplexed rgb (24-bit color) input (?i? multiplex scheme) 0110 8-bit multiplexed rgb (24-bit color) input 0111 8-bit multiplexed rgb (16-bit color) input 1000 8-bit multiplexed rgb (15-bit color) input 1001 8-bit multiplexed ycrcb (normal) input (y, cr and cb multiplexed) 101x 8-bit multiplexed ycrcb (cr and cb shift 128) input (y, cr and cb multiplexed) 110x 8-bit multiplexed ycrcb (y shift 16) input (y, cr and cb multiplexed) 111x 8-bit multiplexed ycrcb (y shift 16 and cr and cb shift 128) input (y, cr and cb multiplexed) offset 01 ? input sync format......................................... rw 7 reserved ........................................always reads 0 6 field signal polarity 0 active low ............................................default 1 active high 5 ds_bco pin control 0 bco output ...........................................default 1 ds input 4 detect embedded sync 0 don?t detect............................................default 1 sync will be detected from the embedded codes on the pixel input stream 3 vertical sync direction 0 input ....................................................default 1 output 2 horizontal sync direction 0 input ....................................................default 1 output 1 vertical sync polarity 0 active low ............................................default 1 active high 0 horizontal sync polarity 0 active low ............................................default 1 active high
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 8- register descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect offset 02 ? scaling / chroma filter control .................. rw 7-6 reserved ........................................ always reads 0 5-3 scaling ratio 000 1/1 .................................................... default 001 3/4 010 5/4 011 5/6 100 7/8 101 7/10 2 reserved ........................................ always reads 0 1-0 chroma channel deflicker adjust 00 no deflicker filter ................................ default 01 1:1:1 deflicker filter 1x 1:2:1 deflicker filter offset 03 ? luma filter control...................................... rw 7-2 reserved ........................................ always reads 0 1-0 luma channel deflicker adjust 00 no deflicker filter ................................ default 01 1:1:1 deflicker filter 1x 1:2:1 deflicker filter offset 04 ? output mode ................................................. rw 7 reserved ........................................ always reads 0 6 ycbcr to yuv conversion 0 disable................................................... default 1 enable 5 reserved ........................................ always reads 0 4 pal_n mode 0 disable................................................... default 1 enable (bits 1-0 must be 00b) 3 pal_nc mode 0 disable................................................... default 1 enable (bits 1-0 must be 00b) 2 reserved ........................................ always reads 0 1 output line selection 0 625 .................................................... default 1 525 0 output tv standard 0 pal .................................................... default 1 ntsc offset 05 ? control 1......................................................... rw 7 reserved ........................................always reads 0 6 master / slave clock mode select 0 master clock mode ...............................default 1 slave clock mode 5 reserved ........................................always reads 0 4 fsci auto adjust 0 disable ...................................................default 1 fsci auto adjust enable, use 14.31818 mhz to calculate fsci [31:0] 3 fsci auto fine tune 0 disable ...................................................default 1 enable 2 pclk clock polarity 0 ....................................................default 1 1-0 pclk output mode 00 1x ....................................................default 01 2x 1x 3x offset 06 ? control 2......................................................... rw 7 color bar 0 disable ...................................................default 1 enable 6-5 xclk input clock mode 00 1x ....................................................default 01 2x 1x 3x 4 edge used to latch input data 0 ....................................................default 1 3-0 input clock adjust 0000 ....................................................default ? 1111 offset 07 ? start active video ......................................... rw 7-0 start active video bits 7-0 ...................default = 00h sets the delay from the leading edge of horizontal sync to start of active video. see rx1c[3] for bit-8. offset 08 ?start horizontal position ............................... rw 7-0 start horizontal position bits 7-0 .......default = 00h used to shift the displayed tv image in a horizontal direction. see rx1c[2] for bit-8. offset 09 ? start vertical position................................... rw 7-0 start vertical position bits 7-0 ............default = 00h used to shift the displayed tv image in a vertical direction. see rx1c[1] for bit-8.
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 9- register descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect offset 0a ? cr amplitude factor.................................... rw 7-0 cr amplitude factor ............................ default = 00h offset 0b ? black level.................................................... rw 7-0 black level .......................................... default = 00h offset 0c ? luma amplitude factor .............................. rw 7-0 luma amplitude factor .......................... default = 0 offset 0d ? cb amplitude factor ................................... rw 7-0 cb amplitude factor ............................... default = 0 offset 0e ? power management...................................... rw 7-4 reserved ........................................ always reads 0 3 dac sense 0 disable................................................... default 1 enable 2 reserved ........................................ always reads 0 1 s-video dac power state 0 on.......................................................... default 1 off 0 composite dac power state 0 on .................................................... default 1 off offset 0f ? status...............................................................ro 7 macrovision copy protection 0 disable ...................................................default 1 enable 6 reserved ........................................always reads 0 5-3 ms_pos 0 ....................................................default 1 2 yt 0 ....................................................default 1 1 ct 0 ....................................................default 1 0 cvbst 0 ....................................................default 1
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 10- register descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect offset 10 ? special effect 0 .............................................. rw 7-0 hue adjust bits 7-0 (see rx11[7-5]) .... default = 00h offset 11 ? special effect 1 ............................................. rw 7-5 hue adjust bits 10-8 (see rx10) ........ default = 000b 4 reserved ........................................ always reads 0 3 dot crawl 0 enable.................................................... default 1 disable 2-0 reserved ........................................ always reads 0 offset 12 ? pll p2 value ................................................ rw 7-4 reserved ........................................ always reads 0 3-0 second post divider control ................... default = 0 offset 13 ? pll d value (05h) ........................................ rw 7-5 resister selection bits 2-0 (see rx15[0]) . default = 0 4-0 pre-divider control ....................... default = 00101b offset 14 ? pll n value (21h) ........................................ rw 7-0 vco output division factor bits 7-0 (see rx15[1] for bit-8) .......................... default = 21h offset 15 ? pll overflow (04h)...................................... rw 7-6 reserved ........................................ always reads 0 5-2 first post divider control ............... default = 0001b 1 vco output division factor bit-8 (see rx14) .............................................................. default = 0 0 resister selection bit-3 (see rx13[7-5]) .. default = 0 offset 16 ? sub-carrier value 0 ...................................... rw 7-0 sub-carrier value bits 7:0 ..................default = 00h offset 17 ? sub-carrier value 1 ...................................... rw 7-0 sub-carrier value bits 15:8 ................default = 00h offset 18 ? sub-carrier value 2 ...................................... rw 7-0 sub-carrier value bits 23:16 ..............default = 00h offset 19 ? sub-carrier value 3 ...................................... rw 7-0 sub-carrier value bits 31:24 ..............default = 00h offset 1b ? version id.......................................................ro 7-0 version id (vid) ..........................always reads 02h offset 1c ? overflow ........................................................ rw 7-4 reserved ........................................always reads 0 3 start active video bit-8 (see rx7) .............default=0 2 start horizontal position bit-8 (see rx8) .default=0 1 start vertical position bit-8 (see rx9) .....default=0 0 reserved ........................................always reads 0
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 11- register descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect offset 1d ? test 0 .............................................................. ro 7 software reset: 0: reset 6-4 scaler and deflicker test 000 normal................................................... default 001 bist_en:1:bist enable 01x -reserved- 1x1 scale test mode 0 (vsi, hsi, pdi[15:12], pdi[11:0]) 11x scale test mode 1 (vsi, hsi, pdi[15:12], pdo[11:0]) 3-2 encoder test (vsi, hsi, dsi, pdi[15:8], pdo[4:0]) 00 normal................................................... default 01 chrominance test 10 luminance test 11 composite test 1 internal register parallel testing (read mode) (pdo[7:0]) 0 disable................................................... default 1 enable 0 internal register parallel testing (write mode) (pdi[14:0]) 0 disable................................................... default 1 enable offset 1e ? test 1.............................................................. rw 7 test tv out 0 .................................................... default 1 6 turn on input clock mode 0 .................................................... default 1 5 csync output enable 0 output mode.......................................... default 1 4 pd[15:12] bus 0 input mode ............................................ default 1 output mode 3 pd[11:8] bus 0 input mode ............................................ default 1 output mode 2 pd[7:4] bus 0 input mode ............................................ default 1 output mode 1 pd[3:0] bus 0 input mode ............................................ default 1 output mode 0 test input pad 0 .................................................... default 1 offset 1f ? test 2 .............................................................. rw 7-6 y dac control 00 normal function .....................................default 01 dac off 10 test dac 11 invert test dac 5-4 c dac control 00 normal function .....................................default 01 dac off 10 test dac 11 invert test dac 3-2 composite dac control 00 normal function .....................................default 01 dac off 10 test dac 11 invert test dac 1-0 test i2c 0 ....................................................default 1
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 12- register descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect offset 20 ? tv sync step ................................................. rw 7-0 tv sync step ........................................ default = 00h step value to control the shape / slope of the sync. the msb is defined in tv signal overflow register rx24[0]. offset 21 ? tv burst envelope step ............................... rw 7-0 tv burst envelope step ...................... default = 00h step value to control the shape / slope of the burst. the msb is defined in tv signal overflow register rx24[1]. offset 22 ? tv sub-carrier phase adjustment ............. rw 7-0 tv sub-carrier phase adjustment .... default = 00h step value to control the shape / slope of the burst. the msbs are defined in tv signal overflow register rx24[4-2]. offset 23 ?tv blank level............................................... rw 7-0 tv blank level ..................................... default = 00h step value to control the base level of the blank signal. the msb is defined in tv signal overflow register rx24[5]. offset 24 ? tv signal overflow ...................................... rw 7-6 reserved ........................................ always reads 0 5 bit[8] of tv blank level .......................... default = 0 4-2 bit[10:8] of sub-carrier phase adjustment .............................................. default = 0 1 bit[8] of tv burst envelope step ........... default = 0 0 bit[8] of tv sync step (rx20) ................. default = 0 offset 4a ? input aperture threshold ........................... rw 7-0 input data threshold ........................... default = 00h offset 4b - input aperture delta ................................... rw 7-0 input data adjustment value ............. default = 00h offset 4c ? aperture upper threshold.......................... rw 7-0 text enhancement upper threshold .. default = 00h offset 4d ? aperture lower threshold.......................... rw 7-0 text enhancement lower threshold . default = 00h offset 4e ? aperture mode ............................................. rw 7 aperture mode 0 normal................................................... default 1 inverse 6-0 adjustment delta ...................................... default = 0 offset 4f ? coring function ............................................ rw 7 coring function 0 disable ...................................................default 1 enable 6-0 coring function threshold .....................default = 0 offset 50 ? y delay control ............................................. rw 7-3 reserved ..............................................always reads 0 2-0 y delay depth ..........................................default = 0 offset 51 ? uv delay control .......................................... rw 7 burst maximum amplitude bit-8 (see rx52) .def=0 6-4 u delay depth ...........................................default = 0 3 y, cb, cr underflow check 0 disable ...................................................default 1 enable 2-0 v delay depth ...........................................default = 0 offset 52 ? burst maximum amplitude .......................... rw 7-0 burst maximum value (see rx51[7]) ......default = 0
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 13- funcitonal descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect f unctional d escription architecture description data capture the 8-bit or 12-bit multiplexed input data is captured by this module and is transferred to 24-bit data for one pixel. color space converter the data from the data capture module is rgb or ycrcb format. this module converts both formats to yuv 422 format. scaler and deflicker this module converts the lines of input pixel data to the appropriate number of output lines for producing a full-screen image on the television receiver. the image can be scaled to 100% within the viewable area of the screen. the device can perform vertical filtering to reduce the effects of picture flicker due to the interlacing of the output image. because this process trades off vertical resolution in order to reduce flicker, the amount of flicker filtering is programmable and allows the process to be optimized for the specific image. this module finally generates the yuv444 pixel data of the interlaced image to the encoder module. encoder this module accepts the yuv444 pixel data and converts it to a standard baseband television signal that is compatible with worldwide standards including pal (b, d, g, h, i, n, nc, m) and ntsc (m, j). the y data can be manipulated for contrast control and a setup level can be added for brightness control. the u, v data can be scaled to achieve color saturation control. besides, u, v signals are modulated by the appropriate subcarrier sine/cosine waveforms and a phase offset may be added onto the color subcarrier during active video to allow hue adjustment. the resulting u and v signals are added together to make up the chrominance signal. the luma (y) and chroma signals are added together to make up the composite video signal. separated luma and chroma signals make up the s-video signal. dac both vt1621 and VT1621M contain three dacs. each dac is used to convert digital composite or luma / chroma data to analog signals and can be individually powered off if not required. the dac module also has an auto-detection circuit, which provides a way to sense the connection of a tv to either s-video or composite video outputs. data capture color space converter ntsc/ pal encoder dac crtc pll pd[11:0] scaler and deflicker y / r c / g cvbs / b serial bus interface sbd sbc hsync vsync xclk p_out pixel clock horizontal & vertical timing
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 14- funcitonal descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect serial bus interface both vt1621 and VT1621M contain a standard serial bus control port through which the control registers can be written and read. the serial bus address is 40h. crtc normally the vga controller supplies the horizontal and vertical sync signals. however, they could be generated either by the vt1621 or the VT1621M. this module generates the horizontal and vertical sync signals. in ccir656 input mode, the embedded sync may also be used. pll both vt1621 and VT1621M contain a high accuracy, low- jitter phase-locked-loop to create outstanding quality video. normal operation requires the encoding clock to be generated by the pll. in master clock mode, the reference clock of the pll is provided by osc and the frequency is 14.31818 mhz. in slave clock mode, the reference clock is from the xclk pin. master/slave clock mode both vt1621 and VT1621M can be configured either as master or slave clock mode. in master clock mode, the vt1621 and VT1621M provide the pixel clock signal to the video source and expect incoming data to be available when required. in slave clock mode, the vt1621 and VT1621M accept the external pixel clock from the video source. master mode in master clock mode, the vt1621 and VT1621M work as a master and the video source device works as a slave. the vt1621 and VT1621M provide a clock signal thro ugh the pclk pin to the video source device and the video source device will use this clock as a frequency reference. then the video source will generate a clock signal into the xclk pin. the vt1621 and VT1621M will use this clock signal to latch incoming data. the pclk clock signal can also be used as the input clock signal connected directly to the xclk pin. the hsync and vsync signals can be programmed to be either input or output to the tv encoder. the master clock mode can be configured as mode 1 and mode 2 illustrated in figure 3 and figure 4. slave mode in slave clock mode, the vt1621 and VT1621M work as a slave and the video source device works as a master. the video source device will generate a clock signal input to the xclk pin. through the xclk pin, the tv encoder receives a clock from the video source device and uses this clock to latch incoming data. moreover, this clock will be a reference clock of the vt1621 or the VT1621M for generating a pixel clock. the hsync and vsync signals can be programmed to be either input or output to the vt1621 and VT1621M. in slave clock mode, both vt1621 and VT1621M can be configured as illustrated in figure 5. figure 3. master clock mode 1 8/12 data video source device xclk pclk hsync vsync 8/12 data configuration 1 vsync video source device xclk pclk hsync 8/12 data configuration 2 vsync video source device xclk pclk hsync configuration 3 hsync vsync 8/12 data video source device xclk pclk configuration 4 vt1621 or VT1621M vt1621 or VT1621M vt1621 or VT1621M vt1621 or VT1621M
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 15- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect figure 4. master clock mode 2 figure 5. slave clock mode vsync video source device xclk hsync vsync 8/12 data configuration 1 video source device xclk hsync 8/12 data configuration 2 hsync vsync 8/12 data 8/12 data vsync video source device xclk hsync configuration 3 video source device xclk configuration 4 vt1621 or VT1621M vt1621 or VT1621M vt1621 or VT1621M vt1621 or VT1621M video source device xclk hsync vsync 8/12 data configuration 5 hsync vsync 8/12 data video source device xclk configuration 6 8/12 data vsync video source device xclk hsync configuration 7 configuration 8 hsync 8/12 data vsync video source device xclk vt1621 or VT1621M vt1621 or VT1621M vt1621 or VT1621M vt1621 or VT1621M pclk pclk pclk pclk
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 16- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect digital video interface the vt1621 and the VT1621M can both be configured with an 8-bit or 12-bit data bus. it accepts rgb 16-bit, rgb 15- bit, rgb 24-bit or ycrcb 16-bit (ccir 656) data format. 8-bit multiplexed mode ? rgb 15-bit: 5-5-5 over two bytes ? rgb 16-bit: 5-6-5 over two bytes ? rgb 24-bit: 8-8-8 over three bytes ? ycrcb 16-bit: cb, y0, cr, y1 12-bit multiplexed mode ? rgb 24-bit: 8-8-8 over two words figure 6. input interface protocol each rising edge (or each rising and falling edge) of the xclk signal will latch data from the video source device. the multiplexed input data formats are shown in figure 6. the pixel data bus represents an 8 or 12-bit multiplexed data stream, which contains either rgb or ycrcb formatted data. in idf settings 4, 5, 7, 8 and 9, the input data rate is 2x the pixel clock frequency and each pair of p# values (for example, p#a and p#b) will contain a complete pixel, encoded as shown in table 4. when idf = 6, the input data rate is 3x the pixel clock frequency and each triplet of p# values (for example, p#a, p#b and p#c) will contain a complete pixel, encoded as shown in table 4. when the input is ycrcb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as cb, y, cr, y. when idf = 9 (ycrcb 8-bit mode), the h and v sync signals can be embedded into the data stream. in this mode, the embedded sync will follow the ccir656 convention and the first byte of the ?video timing reference code? will be assumed to occur when a cb sample would occur if the video stream is continuous.
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 17- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect table 4. input data format idf 4 24-bit rgb 5 24-bit rgb 6 24-bit rgb 7 16-bit rgb 8 15-bit rgb 9~ 16-bit ycrcb pin p#a p#b p#a p#b p#a p#b p#c p#a p#b p#a p#b p#a p#b pd11 g3 r7 g4 r7 pd10 g2 r6 g3 r6 pd9 g1 r5 g2 r5 pd8 g0 r4 b7 r4 pd7 b7 r3 b6 r3 b7 g7 r7 g2 r4 g2 x cr/cb7 y7 pd6 b6 r2 b5 g7 b6 g6 r6 g1 r3 g1 r4 cr/cb6 y6 pd5 b5 r1 b4 g6 b5 g5 r5 g0 r2 g0 r3 cr/cb5 y5 pd4 b4 r0 b3 g5 b4 g4 r4 b4 r1 b4 r2 cr/cb4 y4 pd3 b3 g7 g0 r2 b3 g3 r3 b3 r0 b3 r1 cr/cb3 y3 pd2 b2 g6 b2 r1 b2 g2 r2 b2 g5 b2 r0 cr/cb2 y2 pd1 b1 g5 b1 r0 b1 g1 r1 b1 g4 b1 g4 cr/cb1 y1 pd0 b0 g4 b0 g1 b0 g0 r0 b0 g3 b0 g3 cr/cb0 y0 # denotes the pixel number video standards there are several bits in the output mode register at offset 04h (see rx4[1-0] and rx4[4-3]) that control the generation of popular video standards. these bits control ntsc and pal video standard encoding parameters. other registers may also need to be modified to meet every video parameter of the particular video standard to be output. video timing diagrams are illustrated in figure 7 through figure 12 which summarize all the common video standards. composite and s-video outputs are supported in either ntsc or pal format. figure 13 through figure 18 illustrate the composite and s-video output waveforms of color test pattern bars.
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 18- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect figure 7. interlaced 525-line (ntsc) video timing
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 19- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect figure 8. interlaced 525-line (pal-m) video timing
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 20- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect figure 9. interlaced 625-line (pal-b, d, g, h, i, nc) video timing (fields 1-4)
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 21- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect figure 10. interlaced 625-line (pal-b, d, g, h, i, nc) video timing (fields 5-8)
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 22- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect figure 11. interlaced 625-line (pal-n) video timing (fields 1-4)
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 23- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect figure 12. interlaced 625-line (pal-n) video timing(fields 5-8)
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 24- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect 26.67 9.08 7.63 0.00 white level black level blank level sync level white yellow green cyan magenta red blue 100 ire 40 ire ma black 7.5 ire 1.000 0.340 0.286 0.000 v figure 13. 525-line (ntsc/pal-m) y (luma) video test pattern waveform 26.67 8.00 0.00 white level black / blank level sync level white yellow green cyan magenta red blue ma black 1.000 0.300 0.000 v figure 14. 625-line (pal-b, d, g, h, i, n, nc) y (luma) test pattern waveform
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 25- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect 28.19 20.86 13.26 5.91 blank level white yellow green cyan magenta red blue ma black 1.047 0.782 0.499 0.217 v 17.05 0.640 color burst (9 cycles) 20 ire 20 ire figure 15. 525-line (ntsc/pal-m) c (chroma) video test pattern waveform 13.08 5.25 0.492 0.195 17.05 0.640 21.05 0.788 28.85 blank level white yellow green cyan magenta red blue ma black 1.079 v color burst (2.22 us) figure 16. 625-line (pal-b, d, g, h, i, n, nc) c (chroma) video test pattern waveform
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 26- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect 7.63 0.00 0.286 0.000 9.08 0.340 11.44 0.428 28.85 blank level white yellow green cyan magenta red blue ma black 1.079 v color burst (9 cycles) 26.67 1.000 3.84 0.145 sync level black level white level 100 ire 40 ire 7.5 ire 34 ire 20 ire 20 ire figure 17. composite 525-line (ntsc/pal-m) video test pattern waveform 4.03 0.00 0.152 0.000 8.00 0.300 12.00 0.448 ma v 26.67 1.000 1.79 0.086 sync level black / blank level white level color burst (2.22 ms) white yellow green cyan magenta red blue black figure 18. composite 625-line (pal-b, d, g, h, i, n,nc) video test pattern waveform
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 27- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect color bar test pattern generator the vt1621 and VT1621M all have a built-in color test pattern generator that produces 75% amplitude and 100% saturation eia colors for ntsc and pal video standards as illustrated in figure 13 through figure 18. subcarrier generation this device uses a 32-bit-word to synthesize the subcarrier. the value of the sub-carrier increment required to generate the desired subcarrier frequency is found with the following equations: ntsc: fsci[31:0] = 2 32 * [455 / (2 * h_total)] -or- fsci[31:0] = (int) (2 32 * 3.579545 / f clk ) pal: fsci[31:0] = 2 32 * [(1135/4 + 1/625) / (h_total)] -or- fsci[31:0] = (int) (2 32 * 4.43361875 / f clk ) the 32-bit sub-carrier value, fsci, is defined in rx16-19. h_total is the number of output pixels desired per line. f clk is the encoder clock frequency if rx5[4]=0 (fsci auto adjust disabled); f clk =14.31818mhz if rx5[4]=1 (fsci auto adjust enabled). this allows the generation of any desired subcarrier for any desired video standard. the 32-bit subcarrier increment fsci[31:0] must be loaded by the serial interface before the subcarrier can be enabled. in order to prevent any residual errors from accumulating, the subcarrier is reset every two lines for the ntsc standard and every field for the pal standard. burst generation subcarrier burst generation is a function of the video standard (e.g. ntsc or pal), the subcarrier frequency increment (fsci), and the burst horizontal begin and end register settings. the burst will automatically be blanked during horizontal sync to prevent invalid sync pulses from being generated. the burst blanking is automatically controlled by the selected video format. the burst rise and fall times can be configured by programming the chip registers. power down mode the vt1621 and VT1621M can be powered down by programming their registers. all register contents are maintained when the tv encoder chip is in power down mode . macrovision anti-copy protection the VT1621M features macrovision 7.1 anti-copy protection. this algorithm modifies the ntsc/pal signals to inhibit recording on vcr devices, while not affecting direct tv viewing. all of the parameters that control the anti-copy protection block are fully programmable. display modes there are a total of 27 display modes. each mode is determined by four factors: input resolution, tv standard, tv lines, and scaling ratio. both vt1621 and VT1621M are designed to accept input resolutions of 640x480, 800x600, 640x400 (including 320x200 scan-doubled output), 720x400, and 512x384. the vt1621 and vt1621 are also designed to support output to either ntsc or pal television standards. the vt1621 and VT1621M all provide interpolated scaling with selectable ratios of 1:1, 3:4, 5:4, 5:6, 7:8 and 7:10 in order to support adjustable overscan or underscan operation when displayed on tv. these combinations of ratios result in a matrix of useful operating modes. pal-m has 525 lines just like ntsc but the horizontal frequency and the frame rate are different from ntsc. therefore, pal-m and ntsc share the same modes but the pixel clock frequency varies. all the modes are listed in table 5 and table 6 below. table 5. display modes for pal (m) mode rx00 [7-5] rx04 [1-0] rx02 [5-3] input format h_total * v_total pixel clock output standard scaling 2 000 10 010 512 x 384 800 x 420 20.160020 pal(m) 5/4 3 000 10 000 512 x 384 784 x 525 24.696025 pal(m) 1/1 6 001 10 010 720 x 400 945 x 420 23.814024 pal(m) 5/4 7 001 10 000 720 x 400 936 x 525 29.484029 pal(m) 1/1 10 010 10 010 640 x 400 840 x 420 21.168021 pal(m) 5/4 11 010 10 000 640 x 400 840 x 525 26.460026 pal(m) 1/1 12 010 10 100 640 x 400 840 x 600 30.240030 pal(m) 7/8 16 011 10 000 640 x 480 784 x 525 24.696025 pal(m) 1/1 17 011 10 100 640 x 480 784 x 600 28.224028 pal(m) 7/8 18 011 10 011 640 x 480 800 x 630 30.240030 pal(m) 5/6 21 100 10 011 800 x 600 1040 x 630 39.312039 pal(m) 5/6 22 100 10 001 800 x 600 1040 x 700 43.680044 pal(m) 3/4 23 100 10 101 800 x 600 1064 x 750 47.880049 pal(m) 7/10 25* 101 10 000 720 x 480 858 x 525 13.513514 pal(m) 1/1
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 28- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect 27* 110 10 000 640 x 400 910 x 525 14.332515 pal(m) 1/1 * interlaced input mode
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 29- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect table 6. display modes for ntsc (m, j) & pal (b, d, g, h, i, n, nc) mode rx00 [7-5] rx04 [1-0] rx02 [5-3] input format h_total * v_total pixel clock output standard scaling 0 000 00 010 512 x 384 840 x 500 21.000000 pal 5/4 1 000 00 000 512 x 384 840 x 625 26.250000 pal 1/1 2 000 11 010 512 x 384 800 x 420 20.139860 ntsc 5/4 3 000 11 000 512 x 384 784 x 525 24.671329 ntsc 1/1 4 001 00 010 720 x 400 1125 x 500 28.125000 pal 5/4 5 001 00 000 720 x 400 1116 x 625 34.875000 pal 1/1 6 001 11 010 720 x 400 945 x 420 23.790210 ntsc 5/4 7 001 11 000 720 x 400 936 x 525 29.454545 ntsc 1/1 8 010 00 010 640 x 400 1000 x 500 25.000000 pal 5/4 9 010 00 000 640 x 400 1008 x 625 31.500000 pal 1/1 10 010 11 010 640 x 400 840 x 420 21.146853 ntsc 5/4 11 010 11 000 640 x 400 840 x 525 26.433566 ntsc 1/1 12 010 11 100 640 x 400 840 x 600 30.209790 ntsc 7/8 13 011 00 010 640 x 480 960 x 500 24.000000 pal 5/4 14 011 11 000 640 x 480 840 x 625 26.250000 pal 1/1 15 011 00 011 640 x 480 840 x 750 31.500000 pal 5/6 16 011 11 000 640 x 480 784 x 525 24.671329 ntsc 1/1 17 011 11 100 640 x 480 784 x 600 28.195804 ntsc 7/8 18 011 11 011 640 x 480 800 x 630 30.209790 ntsc 5/6 19 100 00 000 800 x 600 944 x 625 29.500000 pal 1/1 20 100 00 011 800 x 600 960 x 750 36.000000 pal 5/6 21 100 11 011 800 x 600 1040 x 630 39.272727 ntsc 5/6 22 100 11 001 800 x 600 1040 x 700 43.636364 ntsc 3/4 23 100 11 101 800 x 600 1064 x 750 47.832169 ntsc 7/10 24* 101 00 000 720 x 576 864 x 625 13.500000 pal 1/1 25* 101 11 000 720 x 480 858 x 525 13.500000 ntsc 1/1 26* 110 00 000 800 x 500 1135 x 625 17.734375 pal 1/1 27* 110 11 000 640 x 400 910 x 525 14.318182 ntsc 1/1 * interlaced input mode
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 30- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect filters the y components are low-pass filtered, upsampled and low- pass filtered again (for removing the image of upsampling) with a filter response illustrated in figure 19. the uv components also have the same operations; the filter response is illustrated in figure 20. the pixel clock is different for each display mode. therefore, the filter coefficients should be different for each mode so that the tv encoder can generate a high quality tv image. all the filter coefficients are programmed through the serial bus interface to provide a controllable bandwidth output on both composite and s-video signals. figure 19. luminance lowpass filter response (27 mhz)
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 31- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect figure 20. chrominance lowpass filter response (27mhz)
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 32- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect clock frequency a crystal must be present between the xi and xo pins for generating a 14.31818 mhz reference clock for the pll (phase lock loop). in master clock mode, the pll uses this clock as a reference. in slave mode, the pll uses the clock from the xclk pin as a reference clock. the pll generates 2 clocks: one is pixel clock output on the pclk pin (for master mode use only) and the other is the pixel clock used by the scaler and encoder engines. the frequency is calculated by the following formula: f clk = f refclk * n / (d*p) the settings of the pll control registers are listed in table 3 on page 6. table 7. clock settings mode pixel(mhz) d n p 0 21.000000 2.5 44 12 1 26.250000 2 44 12 2 20.139860 3.5 64 13 3 24.671329 2.5 56 13 4 28.125000 4 55 7 6 23.790210 2.5 54 13 7 29.454545 2.5 36 7 8 25.000000 3.5 55 9 9 31.500000 2 44 10 10 21.146853 2.5 48 13 11 26.433566 6.5 96 8 12 30.209790 6.5 96 7 13 24.000000 3.5 88 15 14 26.250000 3 44 8 15 31.500000 2 44 10 16 24.671329 2.5 56 13 17 28.195804 6.5 128 10 18 30.209790 6.5 96 7 19 29.500000 14.5 239 8 20 36.000000 2.5 44 7 21 39.272727 3.5 48 5 22 43.636364 3.5 32 3 23 47.832169 6.5 152 7 24* 13.500000 2.5 33 14 25* 13.500000 2.5 33 14 27* 14.318180 2 28 14
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 33- functional descriptions technologies, inc. we c onnect w e c onnect we c onnect w e c onnect pc b oard l ayout c onsiderations component placement the tv encoder chip should be close to the video connectors and close to the video source device (e.g. vga controller). all other digital components and high-speed digital signal traces should be located as far away as possible from analog circuits. analog components or analog sections of mixed signal components should be placed directly over the analog power and ground planes and the same applies to the digital counterparts. figure 21. ground plane with 4 layer pcb analog ground digital ground vt1621 ferrite bead ferrite bead
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 34- electrical specifications technologies, inc. we c onnect w e c onnect we c onnect w e c onnect e lectrical s pecifications absolute maximum ratings symbol description min typ max unit t stg storage temperature ?55 125 oc t c case operating temperature 0 55 oc v i input voltage (all digital pins) gnd ? 0.5 vcc+0.5 v v esd electrostatic discharge (human body) 2 kv t vps vapor phase soldering (1 min.) 220 oc recommended operating conditions symbol description min typ max unit vcc33 i/o voltage 2.97 3.3 3.63 v vcc25 digital power supply voltage 2.25 2.5 2.75 v vccpll pll power 2.25 2.5 2.75 v vccdac dac power 2.25 2.5 2.75 v rl output load to dac outputs 37.5 ?
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 35- electrical specifications technologies, inc. we c onnect w e c onnect we c onnect w e c onnect power supply current and total power consumption specifications symbol description min typ max unit i d33 vcc33 10 ma i d25 vcc25 50 ma i aall vccdac + vccpll (concurrent. composite & s-video) 150 ma i asv vccdac + vccpll (s-video only) 120 ma i acomp vccdac + vccpll (composite only) 80 ma p tot total power consumption 533 mw note: (operating conditions: tc = 25oc, rset = 4.87k ? ) dc specifications symbol parameter min typ max unit condition vcc33 i/o voltage 3.0 3.6 v normal op. v il input low voltage ?0.5 0.3 vcc v non 5v tolerant v ih input high voltage 0.7 vcc 1.05 vcc v non 5v tolerant v ih5t input high voltage 0.7 vcc 5.5 v v 5v tolerant v ol output low voltage - 0.1 vcc v i ol = 3.2ma v oh output high voltage 0.7 vcc - v i oh = -200ma i oz input leakage ?10 10 ma 0 < v in < vcc c in input capacitance - 10 pf c out output capacitance - 10 pf
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 36- electrical specifications technologies, inc. we c onnect w e c onnect we c onnect w e c onnect dac dc characteristics parameter min typ max unit frequency 50 mhz output delay 14 ns output rising time 10 ns output falling time 10 ns output settling time 20 ns glitch energy, dac step settling within 1lsb 75 pv*s psrr 45 db dac to dac crosstalk tbd db dac matching tbd % note: (vdda2=2.5v; rl=37.5 ? ; rset=4.87k ? ; temp=60 o c, unless otherwise noted) dac ac characteristics parameter min typ max units frequency 50 mhz output delay 14 ns output rising time 10 ns output falling time 10 ns output settling time 20 ns glitch energy, dac step settling within 1lsb 75 pv*s psrr 45 db dac to dac crosstalk tbd db dac matching tbd % note: (vdda2=2.5v; rl=37.5 ? ; rset=4.87k ? ; temp=60 o c, unless otherwise noted)
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 37- electrical specifications technologies, inc. we c onnect w e c onnect we c onnect w e c onnect display signal characteristics parameters min typ max unit pixel clock width 10 25 ns horizontal sync width 1 tp setup time from pixel data to pixel clock 3 17 ns hold time from pixel clock to pixel data 2 ns pll characteristics operating conditions min typ max unit power supply 2.25 2.75 v clock output duty cycle 45 55 % note: crystal spec: 14.31818mhz ( 50 ppm)
vt1621 / VT1621M tv encoder revision 1.0 june 17, 2002 - 38- electrical specifications technologies, inc. we c onnect w e c onnect we c onnect w e c onnect p ackage m echanical s pecifications figure 22. mechanical specification ? 44-pin tqfp thin quad flat pack control dimensions are in millimeters. symbol millimeter inch min. nom. max. max. min. nom. a a1 a2 d d1 e e1 r2 r1 c l l1 s b e aaa bbb ccc ddd d2 e2 tolerances of form and position 12.00 bsc. 10.00 bsc. 12.00 bsc. 10.00 bsc. 0.472 bsc. 0.393 bsc. 0.472 bsc. 0.393 bsc. 0.05 0.95 1.00 1.20 0.15 1.05 0 0 11 11 3.5 12 12 7 13 13 0.08 0.08 0.20 0.003 0.003 0.008 0 0 11 11 3.5 12 12 7 13 13 0.047 0.006 0.041 0.039 0.002 0.037 0.20 0.20 0.10 0.20 0.008 0.008 0.004 0.008 0.80 bsc. 8.00 8.00 0.031 bsc. 0.315 0.315 1.00 ref 0.039 ref 0.09 0.45 0.20 0.22 0.60 0.30 0.20 0.75 0.38 0.004 0.018 0.008 0.009 0.024 0.012 0.008 0.030 0.015 0 - 0 2 - 0 3 - 0 1 - notes : 1. 2. 3. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar can not be located on the lower radius or the foot. minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. dimension "b" different from jedec spec: ase: 0.22 / 0.30 / 0.38 jedec: 0.30 / 0.37 / 0.45 seating plane c c ccc 0 1 - 0 - a a2 a1 l1 c e 0.05 b d d1 d2 a e e1 e2 b d ab b ad d c h aaa bbb ddd 4x 4x mc b a ss d s gage plane r1 r2 0.25mm sl 0 3 - 0 2 - h part number date code, chip revision and country of assembly lot code vt1621 yywwrr taiwan lllllllll c m

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